06056: osborne1: osborne1 banking doesn't work properly

ID	Category [?]	Severity [?]	Reproducibility	Date Submitted	Last Update
06056	Gameplay	Major	Always	Oct 28, 2015, 13:50	Oct 29, 2015, 11:57

Tester	cuavas	View Status	Public	Platform	MESS (Official Binary)
Assigned To	cuavas	Resolution	Fixed	OS	Windows Vista/7/8 (64-bit)
Status [?]	Resolved			Driver	osborne/osborne1.cpp
Version	0.166	Fixed in Version	0.168	Build	Normal
		Fixed in Git Commit		Github Pull Request #

Summary	06056: osborne1: osborne1 banking doesn't work properly
Description	Osborne 1 can switch between ROM and memory mapped I/O or RAM in the low 16k of the address space. The logic to do this is rather convoluted, and involves several flipflops. From the schematic the following signals are significant in the selection of this bank: RESET* <= power-on reset generator NMI* <= reset key active low M1* <= (/M1 == 1) M1 <= (/M1 == 0) INTAK* <= (/IORQ == 0) && (/M1 == 0) && (/WR == 1) MREQ* <= (/MREQ == 1) \|\| (/RFSH == 0) RD* <= (/RD == 1) ROM RD* <= (MREQ* == 1) \|\| (RD* == 1) /NMI <= (NMI* == 1) \|\| (UB6-5 == 1) UB6-5 (flipflop) write to 0x01 in I/O => 1 M1 0->1 => NMI* (i.e. set by writing to port 1 or the start of opcode fetch or interrupt acknowledge while reset key is not pressed, and cleared by start of opcode fetch or interrupt acknowledge while reset key is pressed) UB4-5 (flipflop) Write to 0x01 in I/O => 1 (INTAK* == 0) => 0 ((M1 == 1) \|\| (ROM MODE* == 0)) 0->1 => UB6-5 ROM MODE* (flipflop) write to 0x01 in I/O => 1 (write to 0x00 in I/O) \|\| (RESET* == 0) => 0 ((M1 == 1) \|\| (ROM MODE* == 0)) 0->1 => UB4-5 ROM CE* <= (ROM MODE* == 1) \|\| (ADDR15 == 1) \|\| (ADDR14 == 1) \|\| (ADDR15 == 1) IO REQ <= (ROM MODE* == 0) && (ADDR15 == 0) && (ADDR14 == 0) && (ADDR13 == 1) && (MREQ* == 0) I/O SEL* (flipflop) (I/O REQ == 0) => 1 CPU CLK 0->1 => (CHAR CLK* == 0) \|\| (MEM CLK == 0) The ROM MODE* signal is the key one. Note the nasty feedback loops in the way flipflops are set. To handle banking properly, we need to track the UB6-5, UB4-5 an ROM MODE* flipflop values. The following signals need to be available: * I/O space writes (we get a nice callback for this already) * RESET* (power-on reset can be done in the device reset handler) * NMI* (comes from a currently unimplemented button, but simple enough) * /M1 output of Z80 CPU (not sure if this is available, need to detect edges) * /IORQ and /WR output of Z80 CPU (only used in conjunction with /M1 to detect interrupt acknowledge, level sensitive but we need the edge to trigger the transition)
Steps To Reproduce
Additional Information
Github Commit

Flags
Regression Version
Affected Sets / Systems	osborne1

Attached Files

No.12094 galibert Developer Oct 28, 2015, 14:05	On the z80, M1-active fetches are done from the DECRYPTED_OPCODES map, all the other memory accesses from the PROGRAM map. Interrupt ack has its own callback now. So it's not as immediate as having direct signal callbacks, but the information is there and the semantics probably make sense. OG.
No.12095 galibert Developer Oct 28, 2015, 14:06	Oh, and there's a callback on refresh too.